Barnouti, N.H., Al-Dabbagh, S.S.M, Matti, W.E, & Naser, M.A.S. (2016). Face detection and recognition using Viola-Jones with PCA-LDA and square euclidean distance. International Journal of Advanced Computer Science and Applications, 7(5), (pp. 371-377)
Betz, V. & Rose, J. (1997). VPR: A new packing, placement and routing tool for FPGA. In International Workshop on Field Programmable Logic and Applications. London, (pp. 213-222).
Chen, S.C. & Chang, Y.W. (2017). FPGA placement and routing. IEEE ACM International Conference on Computer-Aided Design (ICCAD).
Clarke J.A., Gaffar, A.A, Constantinides, G.A., & Cheung, P.Y.K. (2006). Fast word-level power models for synthesis of FPGA-based arithmetic. IEEE International Symposium on Circuits and Systems.
Das P., Chatterji B. (1990). Orthogonal distances for digital pictures. Information Sciences, 50, (pp. 123-150).
Deschamps, J.P, Bioul, G. (2006). Synthesis of arithmetic circuits FPGA, ASIC, and embedded systems. John WILEY & SONS.
Dossis, M. (2011). Formal generation of synthesizable RTL from regular programs. 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).
Feng, Q., Yuan, C., Pan, J.S., Yang, J.F., Chou, Y.T., & Zhou, Y. (2017, February). Superimposed Sparse Parameter Classifiers for Face Recognition. IEEE Transactions on Cybernetics. 47(2), (pp. 378-390)
Jaafar, A. Soin, N. and Hatta, N. (2017). An educational FPGA design process flow using Xilinx ISE 13.3 project navigator for students. IEEE 13th International Colloquium on Signal Processing & its Applications (CSPA)
Lyalin, A. (2007). Formal methods of algorithm analysis for decreasing RTL verification complexity. 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics.
Melter R. (1991). A survey of digital metrics. Vision Geometry Contemporary Mathematics. Contemporary Mathematics, 119, (pp. 95-106).
Masato-Inagi, M., Takashima, Y., Nakamura, Y. (2010). Globally optimal time-multiplexing of inter-FPGA connections for multi-FPGA prototyping systems. IPSJ Transactions on System LSI Design Methodology.
Pistorius, J. & Hutton. M. (2003). Placement rent exponent calculation methods, temporal behaviour and fpga architecture evaluation. SLIP’03: Procedings of the 2003 International Worhshop on System Level Interconnect Prediction, (pp. 31-38).
Rodrequez-Andina, J.J., Moure, M.J., & Valdes, M.D. (2007). Features, design tools, and application domains of FPGA. IEEE Transactions on Industrial Electronics, 54(4).
Salcic, Z. (2001). Synthesizing Logic From VHDL Description. VHDL and FPLDs in Digital Systems Design, Prototyping and Customization.
Siguenza-Tortosa, D. and Nurmi, J. (2002). VHDL Based simulation environment for proteo NoC. Seventh IEEE International. High-Level Design Validation and Test Workshop, 1(6), (pp. 27-29).
Skliarova, I. & Ferrari, A.B. (2000). Exploiting FPGA-based architectures and design tools for problems of reconfigurable computations. Proceedings 13th Symposium on Integrated Circuits and Systems Design. Computer Science.
Taraate, V. (2017). Design and simulation using VHDL constructs. PLD Based Design with VHDL – RTL Design, Synthesis and Implementation. Springer Edition.
Tang, Q. Mehrez, H. and Tuna, M. (2013). Routing algorithm for Multi-FPGA based systems using multi-point physical tracks. International Symposium on Rapid System Prototyping (RSP).
Yuhui, Z., Byeungwoo, J., Danhua, X., Jonathan, W.Q.M., & Hui, Z. (2015). Image segmentation by generalized hierarchical fuzzy C-means algorithm. Journal of Intelligent & Fuzzy Systems, 28(2), (pp. 961-973).
Pentland, A., Moghaddam, B. and Starner, T. (1994, Jun). View-based and modular eigenspaces for face recognition. Computer Vision and Pattern Recongnition. Proceedings CVPR’94, IEEE Computer Society Conference, (pp. 84-91).
Jian, Y., Zhang, D., Frangi, A. and Y. Yang, J. (2004, January). Two-Dimensional PCA: A new approach to appearance-based face representation and recognition. IEEE Transactions on Pattern Analysis and Machine Intelligence, 26(1), (pp. 131–137).
Monmasson, E., & Cirstea, M. N. (2007, August). FPGA design methodology for industriel control systems. A review IEEE Transactions on Industrial Electronics, 54(4).
Morizet, N. (2009, March). Biometric Recognition by Multimodal Fusion of Face and Iris. PhD thesis, specialty: Signal and Images. National School of Telecommunications. Paris, France.
Alfke, P. (2009, August). Xilinx Virtex-6 and SPARTAN-6 FPGA families. IEEE Hot Chips 21 Symposium (HCS).
Li Jun, L. & Wei, W. (2010, November). PCI express interface design and verification based on SPARTAN-6 FPGA. IEEE 12th International Conference on Communication Technology.
Bezerra, E. & Lettnin, D. (2013, October). Writing Synthesizable VHDL Code for FPGA. Synthesizable VHDL Design for FPGA.
Komulainen, J., Hadid, A., & Pietikäinen, M. (2014, January). Context based face anti-spoofing. 2013 IEEE Sixth International Conference on Biometrics: Theory, Applications and Systems (BTAS), Arlington, VA, USA.
Boulkenafet, Z., Komulainen, J., & Hadid, A. (2016, August). Face Spoofing Detection Using Colour Texture Analysis. IEEE Transactions on Information Forensics and Security, IEEE Biometrics Compendium, 11(8), (pp. 1818-1830)
Alaslani, M.G., & Elrefaei, L.A. (2018, April). Convolutional neural network based feature extraction for iris recognition. International Journal of Computer Science and Information Technology (IJCSIT), 10(2), (pp. 65-78).
Challouf, M. and Hicham, M. (2007). Tutorial Xilinx ISE 9.1. INSAT Tunis.